# HDLbits第一天

## Getting Started

### Step one

We want to assign 1 to the output one.

``````module top_module( output one );

assign one = 1'b1;

endmodule
``````

## Output Zero

### Zero

Fun fact: For Quartus synthesis, not assigning a value to a signal usually results in 0. This problem is actually easier than the previous one.

``````module top_module(
output zero
);// Module body starts after semicolon
assign zero = 1'b1;
endmodule
``````

## Verilog Language

### Basic

#### Simple wire

A continuous assignment assigns the right side to the left side continuously, so any change to the RHS is immediately seen in the LHS.

``````module top_module( input in, output out );
assign out = in;
endmodule
``````

#### Four wire The concatenation operator { signal1, signal2, signal3, ... } would be useful here.

``````module top_module(
input a,b,c,
output w,x,y,z );

assign w = a;
assign x = b;
assign y = b;
assign z = c;

endmodule
``````

#### Inverter Notgate
Verilog has separate bitwise-NOT (~) and logical-NOT (!) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

``````module top_module( input in, output out );

assign out = ~in;

endmodule
``````

#### AND gate Andgate
Verilog has separate bitwise-AND (&) and logical-AND (&&) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

``````module top_module(
input a,
input b,
output out );

assign out = a && b;

endmodule
``````

#### NOR gate Norgate
Verilog has separate bitwise-OR (|) and logical-OR (||) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

``````module top_module(
input a,
input b,
output out );

assign out = ~(a || b);

endmodule
``````

#### XNOR gate Xnorgate
The bitwise-XOR operator is ^. There is no logical-XOR operator.

``````module top_module(
input a,
input b,
output out );

assign out = ~(a ^ b);

endmodule
``````

#### Declaring wires Wire decl

```````default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n   );

wire w1;
wire w2;

assign w1 = a && b;
assign w2 = c && d;
assign out = w1 || w2;
assign out_n = ~(w1 || w2);

endmodule
``````

#### 7458 chip 7458
You need to drive two signals (p1y and p2y) with a value.

``````module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );

assign p2y = (p2a && p2b) || (p2c && p2d);
assign p1y = (p1a && p1c && p1b) || (p1f && p1e && p1d);

endmodule
``````