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HDLbits第一天


发布时间: 2022-11-24 22:26:00    浏览次数:30 次

出于对FPGA学习巩固的目的,同时也希望能锻炼自己对于Verilog的题目分析,让自己对HDL代码的理解加深,所以想坚持写一下关于HDLbits网站刷题的系列,计划是工作日每日5题目+分析,周末每日十题+分析(如果题目繁琐会减轻数量,以能够分析准确并理解为主)


Getting Started

Step one

We want to assign 1 to the output one.

module top_module( output one );

// Insert your code here
    assign one = 1'b1;

endmodule

第一题就是简单的进行一个输出的设置。

Output Zero

Zero

Fun fact: For Quartus synthesis, not assigning a value to a signal usually results in 0. This problem is actually easier than the previous one.

module top_module(
    output zero
);// Module body starts after semicolon
	assign zero = 1'b1;
endmodule

其实就是和上一个题一样只不过需要自己写出assign这个赋值语句,其实assign描述的就是连线。

Verilog Language

Basic

Simple wire

A continuous assignment assigns the right side to the left side continuously, so any change to the RHS is immediately seen in the LHS.

module top_module( input in, output out );
	assign out = in;
endmodule

使用assign赋值语句简单的将两个变量相连。

Four wire

image.png
The concatenation operator { signal1, signal2, signal3, ... } would be useful here.

module top_module( 
    input a,b,c,
    output w,x,y,z );

    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
    
endmodule

这个题说明的就是多个赋值语句的处理。

Inverter

image.png
Notgate
Verilog has separate bitwise-NOT (~) and logical-NOT (!) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( input in, output out );

    assign out = ~in;
    
endmodule

构建非门

AND gate

image.png
Andgate
Verilog has separate bitwise-AND (&) and logical-AND (&&) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a && b;
    
endmodule

构建与门

NOR gate

image.png
Norgate
Verilog has separate bitwise-OR (|) and logical-OR (||) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a || b);
    
endmodule

构建或非门

XNOR gate

image.png
Xnorgate
The bitwise-XOR operator is ^. There is no logical-XOR operator.

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a ^ b);
    
endmodule

构建异或非门

Declaring wires

image.png
Wire decl

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 

    wire w1;
    wire w2;
    
    assign w1 = a && b;
    assign w2 = c && d;
    assign out = w1 || w2;
    assign out_n = ~(w1 || w2);
    
endmodule

当电路的结构复杂的时候可以使用wire添加中间变量简化编程语句复杂度。

7458 chip

image.png
7458
You need to drive two signals (p1y and p2y) with a value.

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    assign p2y = (p2a && p2b) || (p2c && p2d);
    assign p1y = (p1a && p1c && p1b) || (p1f && p1e && p1d);
    
endmodule

和其他的编程语言一样啊,过于复杂用括号就能简化语句防止出错。

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